4 · Processor Fundamentals
4.1 CPU Architecture — Von Neumann, registers, ALU/CU/clock/IAS, buses, performance factors, ports, the Fetch–Execute cycle, interrupts. 4.2 Assembly Language — machine code, the two-pass assembler, tracing, instruction groups, addressing modes. 4.3 Bit manipulation — binary shifts and masking.
🧩 Jigsaw
122 concepts mapped to the syllabus
🎯 Pack
114 question/answer pairs
| 9618 tested | 9608 only | Untested | From SME | |
|---|---|---|---|---|
| Jigsaw | 73 | 0 | 32 | 17 |
| Pack | 72 | 0 | 29 | 13 |
What to know about this topic
The only topic with zero 9608 entries
9618 rebuilt this topic so thoroughly that the old Legend contributes nothing usable — and 4.3 Bit manipulation has no 9608 questions whatsoever (its Legend file is two pages with none). Bit manipulation is nonetheless examined in every single series. There is no old-syllabus safety net anywhere in this chapter.
Cyclic shifts — named in the syllabus, examined zero times
The notes name “logical, arithmetic and cyclic”. Logical shifts appear every series and arithmetic shifts twice recently; cyclic shifts have never been examined, and there is no 9608 fallback. The single clearest gap in the chapter.
Every RTN question stops at the fetch
The bullet is titled stages of the Fetch–Execute cycle, and the syllabus says “describe and use register transfer notation”. Yet every 9618 question stops at
CIR ← [MDR]— the fetch only. The decode and execute stages in RTN have never been asked.
Source material
- 9618 — CPU Architecture · 9618 — Assembly Language · 9618 — Bit manipulation
- 9608 — CPU Architecture · 9608 — Assembly Language
⬅ 3 · Hardware · ➡ 5 · System Software · 🧩 Architecture