Show understanding of the basic Von Neumann model for a computer system and the stored program concept
9608_w17_qp_12_sc_4.a
9608_w17_qp_12_sc_4.a Question Image Answer
9608_w17_qp_12_sc_4.a Mark Scheme Image
9608_s15_qp_13_sc_5.a
9608_s15_qp_13_sc_5.a Question Image Answer
9608_s15_qp_13_sc_5.a Mark Scheme Image
Show understanding of the purpose and role of registers, including the difference between general purpose and special purpose registers
9608_s21_qp_12_sc_2
9608_s21_qp_12_sc_2 Question Image Answer
9608_s21_qp_12_sc_2 Mark Scheme Image
9608_s21_qp_11_sc_3.d
9608_s21_qp_11_sc_3.d Question Image Answer
9608_s21_qp_11_sc_3.d Mark Scheme Image
9608_s20_qp_11_sc_6.b
9608_s20_qp_11_sc_6.b Question Image Answer
9608_s20_qp_11_sc_6.b Mark Scheme Image
9608_w19_qp_11_sc_1.a
9608_w19_qp_11_sc_1.a Question Image Answer
9608_w19_qp_11_sc_1.a Mark Scheme Image
9608_w18_qp_13_sc_6.a.i
9608_w18_qp_13_sc_6.a.i Question Image Answer
9608_w18_qp_13_sc_6.a.i Mark Scheme Image
9608_s18_qp_13_sc_3.b
9608_s18_qp_13_sc_3.b Question Image Answer
9608_s18_qp_13_sc_3.b Mark Scheme Image
9608_s18_qp_11_sc_8.a
9608_s18_qp_11_sc_8.a Question Image Answer
9608_s18_qp_11_sc_8.a Mark Scheme Image
9608_s18_qp_11_sc_8.b.i
9608_s18_qp_11_sc_8.b.i Question Image Answer
9608_s18_qp_11_sc_8.b.i Mark Scheme Image
9608_s18_qp_11_sc_8.b.ii
9608_s18_qp_11_sc_8.b.ii Question Image Answer
9608_s18_qp_11_sc_8.b.ii Mark Scheme Image
9608_s16_qp_12_sc_3.a
9608_s16_qp_12_sc_3.a Question Image Answer
9608_s16_qp_12_sc_3.a Mark Scheme Image
9608_s16_qp_11_sc_3.a
9608_s16_qp_11_sc_3.a Question Image Answer
9608_s16_qp_11_sc_3.a Mark Scheme Image
9608_s16_qp_11_sc_9.a.ii
9608_s16_qp_11_sc_9.a.ii Question Image Answer
9608_s16_qp_11_sc_9.a.ii Mark Scheme Image
9608_w15_qp_13_sc_2.b
9608_w15_qp_13_sc_2.b Question Image Answer
9608_w15_qp_13_sc_2.b Mark Scheme Image
9608_w15_qp_11_sc_2.b
9608_w15_qp_11_sc_2.b Question Image Answer
9608_w15_qp_11_sc_2.b Mark Scheme Image
9608_s15_qp_13_sc_5.c
9608_s15_qp_13_sc_5.c Question Image Answer
9608_s15_qp_13_sc_5.c Mark Scheme Image
Show understanding of the purpose and roles of the Arithmetic and Logic Unit (ALU), Control Unit (CU) and system clock, Immediate Access Store (IAS)
9608_w21_qp_11_sc_6.a
9608_w21_qp_11_sc_6.a Question Image Answer
9608_w21_qp_11_sc_6.a Mark Scheme Image
9608_s18_qp_13_sc_3.a
9608_s18_qp_13_sc_3.a Question Image Answer
9608_s18_qp_13_sc_3.a Mark Scheme Image
9608_w17_qp_13_sc_4.a
9608_w17_qp_13_sc_4.a Question Image Answer
9608_w17_qp_13_sc_4.a Mark Scheme Image
9608_w17_qp_12_sc_4.a
9608_w17_qp_12_sc_4.a Question Image Answer
9608_w17_qp_12_sc_4.a Mark Scheme Image
Show understanding of how data are transferred between various components of the computer system using the address bus, data bus and control bus
9608_w21_qp_11_sc_6.a
9608_w21_qp_11_sc_6.a Question Image Answer
9608_w21_qp_11_sc_6.a Mark Scheme Image
9608_w19_qp_11_sc_1.b.i
9608_w19_qp_11_sc_1.b.i Question Image Answer
9608_w19_qp_11_sc_1.b.i Mark Scheme Image
9608_w19_qp_11_sc_1.b.ii
9608_w19_qp_11_sc_1.b.ii Question Image Answer
9608_w19_qp_11_sc_1.b.ii Mark Scheme Image
9608_w18_qp_12_sc_4.c
9608_w18_qp_12_sc_4.c Question Image Answer
9608_w18_qp_12_sc_4.c Mark Scheme Image
9608_w17_qp_13_sc_4.a
9608_w17_qp_13_sc_4.a Question Image Answer
9608_w17_qp_13_sc_4.a Mark Scheme Image
9608_w17_qp_12_sc_4.a
9608_w17_qp_12_sc_4.a Question Image Answer
9608_w17_qp_12_sc_4.a Mark Scheme Image
9608_w15_qp_13_sc_2.a
9608_w15_qp_13_sc_2.a Question Image Answer
9608_w15_qp_13_sc_2.a Mark Scheme Image
9608_w15_qp_11_sc_2.a
9608_w15_qp_11_sc_2.a Question Image Answer
9608_w15_qp_11_sc_2.a Mark Scheme Image
9608_s15_qp_13_sc_5.a
9608_s15_qp_13_sc_5.a Question Image Answer
9608_s15_qp_13_sc_5.a Mark Scheme Image
Show understanding of how factors contribute to the performance of the computer system
9608_w19_qp_11_sc_1.b.ii
9608_w19_qp_11_sc_1.b.ii Question Image Answer
9608_w19_qp_11_sc_1.b.ii Mark Scheme Image
9608_w17_qp_12_sc_4.b
9608_w17_qp_12_sc_4.b Question Image Answer
9608_w17_qp_12_sc_4.b Mark Scheme Image
9608_s15_qp_12_sc_8.a
9608_s15_qp_12_sc_8.a Question Image Answer
9608_s15_qp_12_sc_8.a Mark Scheme Image
9608_s15_qp_11_sc_8.a
9608_s15_qp_11_sc_8.a Question Image Answer
9608_s15_qp_11_sc_8.a Mark Scheme Image
Understand how different ports provide connection to peripheral devices
9608_s20_qp_13_sc_2.c.i
9608_s20_qp_13_sc_2.c.i Question Image Answer
9608_s20_qp_13_sc_2.c.i Mark Scheme Image
9608_s20_qp_13_sc_2.c.ii
9608_s20_qp_13_sc_2.c.ii Question Image Answer
9608_s20_qp_13_sc_2.c.ii Mark Scheme Image
9608_s20_qp_12_sc_2.c.iii
9608_s20_qp_12_sc_2.c.iii Question Image Answer
9608_s20_qp_12_sc_2.c.iii Mark Scheme Image
9608_s15_qp_12_sc_8.b
9608_s15_qp_12_sc_8.b Question Image Answer
9608_s15_qp_12_sc_8.b Mark Scheme Image
9608_s15_qp_11_sc_8.b
9608_s15_qp_11_sc_8.b Question Image Answer
9608_s15_qp_11_sc_8.b Mark Scheme Image
Describe the stages of the Fetch-Execute (F-E) cycle
9608_w21_qp_11_sc_6.b
9608_w21_qp_11_sc_6.b Question Image Answer
9608_w21_qp_11_sc_6.b Mark Scheme Image
9608_s21_qp_13_sc_3.d
9608_s21_qp_13_sc_3.d Question Image Answer
9608_s21_qp_13_sc_3.d Mark Scheme Image
9608_s20_qp_11_sc_6.b
9608_s20_qp_11_sc_6.b Question Image Answer
9608_s20_qp_11_sc_6.b Mark Scheme Image
9608_s19_qp_12_sc_3.a
9608_s19_qp_12_sc_3.a Question Image Answer
9608_s19_qp_12_sc_3.a Mark Scheme Image
9608_w18_qp_13_sc_6.a.i
9608_w18_qp_13_sc_6.a.i Question Image Answer
9608_w18_qp_13_sc_6.a.i Mark Scheme Image
9608_w18_qp_13_sc_6.a.ii
9608_w18_qp_13_sc_6.a.ii Question Image Answer
9608_w18_qp_13_sc_6.a.ii Mark Scheme Image
9608_w18_qp_12_sc_4.a
9608_w18_qp_12_sc_4.a Question Image Answer
9608_w18_qp_12_sc_4.a Mark Scheme Image
9608_s18_qp_11_sc_8.b.ii
9608_s18_qp_11_sc_8.b.ii Question Image Answer
9608_s18_qp_11_sc_8.b.ii Mark Scheme Image
9608_s16_qp_12_sc_3.a
9608_s16_qp_12_sc_3.a Question Image Answer
9608_s16_qp_12_sc_3.a Mark Scheme Image
9608_s16_qp_11_sc_3.a
9608_s16_qp_11_sc_3.a Question Image Answer
9608_s16_qp_11_sc_3.a Mark Scheme Image
9608_s15_qp_13_sc_5.b.i
9608_s15_qp_13_sc_5.b.i Question Image Answer
9608_s15_qp_13_sc_5.b.i Mark Scheme Image
9608_s15_qp_13_sc_5.b.ii
9608_s15_qp_13_sc_5.b.ii Question Image Answer
9608_s15_qp_13_sc_5.b.ii Mark Scheme Image
9608_s15_qp_13_sc_5.b.iii
9608_s15_qp_13_sc_5.b.iii Question Image Answer
9608_s15_qp_13_sc_5.b.iii Mark Scheme Image
9608_s15_qp_13_sc_5.c
9608_s15_qp_13_sc_5.c Question Image Answer
9608_s15_qp_13_sc_5.c Mark Scheme Image
9608_s15_qp_12_sc_8.c
9608_s15_qp_12_sc_8.c Question Image Answer
9608_s15_qp_12_sc_8.c Mark Scheme Image
9608_s15_qp_11_sc_8.c
9608_s15_qp_11_sc_8.c Question Image Answer
9608_s15_qp_11_sc_8.c Mark Scheme Image
Show understanding of the purpose of interrupts
9608_s19_qp_13_sc_4.c.i
9608_s19_qp_13_sc_4.c.i Question Image Answer
9608_s19_qp_13_sc_4.c.i Mark Scheme Image
9608_s19_qp_13_sc_4.c.ii
9608_s19_qp_13_sc_4.c.ii Question Image Answer
9608_s19_qp_13_sc_4.c.ii Mark Scheme Image
9608_w18_qp_13_sc_6.b
9608_w18_qp_13_sc_6.b Question Image Answer
9608_w18_qp_13_sc_6.b Mark Scheme Image
9608_w18_qp_12_sc_4.b.i
9608_w18_qp_12_sc_4.b.i Question Image Answer
9608_w18_qp_12_sc_4.b.i Mark Scheme Image
9608_w18_qp_12_sc_4.b.ii
9608_w18_qp_12_sc_4.b.ii Question Image Answer
9608_w18_qp_12_sc_4.b.ii Mark Scheme Image
9608_s16_qp_12_sc_3.b
9608_s16_qp_12_sc_3.b Question Image Answer
9608_s16_qp_12_sc_3.b Mark Scheme Image
9608_s16_qp_11_sc_3.b
9608_s16_qp_11_sc_3.b Question Image Answer
9608_s16_qp_11_sc_3.b Mark Scheme Image
9608_s15_qp_13_sc_5.d.i
9608_s15_qp_13_sc_5.d.i Question Image Answer
9608_s15_qp_13_sc_5.d.i Mark Scheme Image
9608_s15_qp_13_sc_5.d.ii
9608_s15_qp_13_sc_5.d.ii Question Image Answer
9608_s15_qp_13_sc_5.d.ii Mark Scheme Image